发明名称 |
Transmission logic parity circuit |
摘要 |
An FET transmission logic parity circuit is disclosed which determines the odd or even status of register bits using zero DC current transmission logic. The circuit has a first two FET devices which propagate the state of the preceding odd or even nodes and the corresponding register bit is logically a zero. A second pair of FET devices switch the state of the odd or even nodes when the corresponding register bit is logically a one. In this manner, the output nodes are statically conditioned to either a first potential or a second potential, depending upon the register bit states and no DC current flows between the first and second potential.
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申请公布号 |
US4451922(A) |
申请公布日期 |
1984.05.29 |
申请号 |
US19810332706 |
申请日期 |
1981.12.21 |
申请人 |
IBM CORPORATION |
发明人 |
DEARDEN, ZIBA T.;PURI, YOGI K. |
分类号 |
G06F11/10;H03M13/00;(IPC1-7):G06F11/10;H04L1/10 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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