发明名称 POLLING ADDRESS SELECTING SYSTEM
摘要 PURPOSE:To prevent the reliability of a titled system from being decreased by performing line control without using many microprocessors in a line processor of double polling system. CONSTITUTION:A control section 16 detects a buffer 8 starting writing of receiving data among 80 sets of buffers 8, a counter 17 generates an address corresponding to a receiving section 7, then an address write control signal is generated in a register 11 or 12, and the address is written in the register 11 or 12. Multiplexers 9, 10 select the buffer designated by an address written in the registers 11, 12, and the receiving data is led to a binary synchronizing adaptor 6 via converting sections 13, 14 and microprocessors 4, 5 respectively. Even if 80 sets of terminal devices exist, the line control is attained only by using two microprocessors.
申请公布号 JPS59100653(A) 申请公布日期 1984.06.09
申请号 JP19820210132 申请日期 1982.11.30
申请人 FUJITSU KK 发明人 SATOU TOSHIO
分类号 G06F13/00;G06F13/12;G06Q50/00;G06Q50/10;G06Q50/34;H04L12/44 主分类号 G06F13/00
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