发明名称 A method and apparatus for coordinating execution of an instruction by a coprocessor.
摘要 The part of the instruction received which indicates the type of the instruction is written to the second processor. The response from the second processor is read. A predetermined task is performed selectively if the response indicates that the task must be performed by the first processor in support of the execution of the instruction by the second processor. If the response indicates an exception condition, the processor acknowledges the exception, before starting the appropriate exception handling procedure. If the response shows that the second processor must finish another action e.g. a computation, before responding to the information, the first processor returns to reading the response of the second processor. Should the response show that the second processor (coprocessor) needs the first processor to effect a function such as evaluating an effective address and transferring an operand from it to the second processor, then the first processor performs that function.
申请公布号 EP0123337(A2) 申请公布日期 1984.10.31
申请号 EP19840200440 申请日期 1984.03.26
申请人 MOTOROLA, INC. 发明人 ZOLNOSKY, JOHN;MOTHERSOLE, DAVID;MACGREGOR, DOUGLAS B.;GRUESS, MICHAEL;GROVES, STANLEY E.;SHAHAN, VAN B.;TIETJEN, DONALD L.
分类号 G06F9/00;G06F9/38;G06F15/16;G06F15/173;G06F15/177 主分类号 G06F9/00
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