Dynamic semiconductor memory device having divided memory cell blocks.

摘要

In a dynamic semiconductor memory device comprising memory cells divided into a plurality of blocks (1-1, 1-2), selectively operable simultaneous write enable circuitry (TP1, R3, Q31, Q31-Q34) performs a write operation simultaneously upon the plurality of blocks, and comparison circuitry (Q35-Q38, R4, R5) compares read data of one block with read data of the other block, thereby carrying out a test more rapidly than is possible with an otherwise comparable prior art device.