发明名称 OPTIMUM BLOCK DETECTOR CIRCUIT
摘要 PURPOSE:To design a small-sized optimum block detector circuit in view of vector information by adding cumulative differences between the actual data and predetermined data from the block with the vector information and by comparing the sum with the reference value. CONSTITUTION:The difference between the data from input block and those from the forecasted block is calculated by subtractor 1 and converted into the length of code corresponding to said difference through code converter circuit 2 to be sent to adder 3. The difference between the foremost datum and that of forecasted block is converted into code having the length corresponding to said difference to generate the output only when such a difference is calculated and in otherwise case, the own output is sent from data delay element 5. The cumulative value for one block through added 3 is latched by the block clock at FF6 and sent to comparator 7 to be compared with the cumulative value for the exisisting optimum block. Selector 8 selects smaller value and sends such a smaller value together with the vector information in the selected block.
申请公布号 JPS6156587(A) 申请公布日期 1986.03.22
申请号 JP19840156613 申请日期 1984.07.27
申请人 FUJITSU LTD 发明人 MAKI SHINICHI;ITO TAKASHI;MATSUDA KIICHI;TSUDA TOSHITAKA
分类号 H04N7/32;(IPC1-7):H04N7/137 主分类号 H04N7/32
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