发明名称 PARALLEL INTERFACE FOR CONTROLLING THE BIDIRECTIONAL DATA TRANSFER BETWEEN AN ASYNCHRONOUS BUS AND A SYNCHRONOUS BUS CONNECTED TO A PLURALITY OF TERMINALS EACH SENDING ITS OWN SYNCHRONISM SIGNAL ONTO SAID SYNCHRONOUS BUS
摘要 <p>Interface of the parallel type controlling data transfer between an asynchronous bus, to which a control processor is connected, and a synchronous bus connected to a plurality of terminals each sending its own synchronism signal on the synchronous bus. The control is effected by causing in a time equal to the shortest period of the synchronism signals at least one transfer from or towards each terminal and possibly a transfer from or towards the control processor. The interface assigns a priority to the transfers from or towards the terminals with respect to the transfers from or towards the control processor, and interrupts these latter transfers at the end of the instruction in progress if it receives a pulse of one of the synchronism signals to start a transfer towards the corresponding terminal. In addition, the interface controls the tranfers relevant to the terminals in time sequence with a fixed priority.</p>
申请公布号 CA1203919(A) 申请公布日期 1986.04.29
申请号 CA19840446872 申请日期 1984.01.16
申请人 CSELT-CENTRO STUDI E LABORATORI TELECOMUNICAZIONI S.P.A. 发明人 APPIANO, SILVANO;DESTEFANIS, PAOLO;POGGIO, CESARE
分类号 G06F13/42;G06F13/12;(IPC1-7):G06F9/46;G06F13/26 主分类号 G06F13/42
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