发明名称 |
SYSTEM ZUR VERARBEITUNG VON SIGNALEN NACH EINEM PYRAMIDEN-ALGORITHMUS IN REALZEIT |
摘要 |
The amount of hardware required to implement a Burt Pyramid or an FSD (filter-subtract-decimate) pyramid analyzer (or synthesizer) stage of a sampled temporal signal representing an n-dimensional information component or (such as a video signal) is substantially reduced by employing a time-synchronized multiplexed analyzer stage to derive (or a time-synchronized multiplexed synthesizer stage that is responsive to) a single serial stream of samples of a predetermined plural number of sub-spectra that are arranged in a predetermined temporal order format with respect to one another in accordance with each of a given set of time synchronized, repetitively generated, serially applied control signals. |
申请公布号 |
DE3628349(A1) |
申请公布日期 |
1987.03.05 |
申请号 |
DE19863628349 |
申请日期 |
1986.08.21 |
申请人 |
RCA CORP. |
发明人 |
FRANK BESSLER,ROGER;HENRY ARBEITER,JAMES;OWEN SINNIGER,JOSEPH |
分类号 |
H04N5/21;G06F15/00;G06F17/10;G06K9/54;G06T1/00;G08C13/00;H03H17/00;H03H17/02;H04N7/26;H04N7/54;(IPC1-7):G06F15/62;G06F7/00 |
主分类号 |
H04N5/21 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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