| 摘要 |
<p>An improved voltage level shifter circuit employs pairs of P and N-channel devices (P5,N6; P6,N8) which are operated in response to control signals (VC1,VC2,VA) to generate a voltage shifted output signal (VLS1, VLSI1) that corresponds in timing and polarity to an input data signal. The P and N-channel devices (P5,N6;P6,N8) interact in latched pairs to maintain logic levels for the output signal (VLS1,VLSI1). The P-channel and N-channel devices (P5,N6;P6,N8) of each pair are disconnected prior to each logic level change for the output signal (VLS1,VLSI1) so that the devices of each pair do not oppose one another in changing the logic level of the output signals (VLS1,VLSI1). </p> |
