| 摘要 |
<p>A CMOS to ECL interface circuit includes first and second p-type field effect transistors (22, 23) each having its gate and drain electrodes interconnected, and third and fourth field effect transistors (21, 24) connected in series with the first and second field effect transistors (22, 23). The third and fourth transistors (21, 22) are respectively p-type and n-type. An input terminal (10) is connected to the gate electrodes of the third and fourth transistors (21, 24) and an output terminal is connected to the drain and source electrodes of the first and second transistors (22, 23), respectively. In operation a CMOS input voltage level of -3 volts causes the provision of an output voltage level of -0.88 volts and a CMOS input voltage level of 0 volts causes a provision of an output voltage level of -1.8 volts by virtue of the body effect operative in the second transistor (23). Two other embodiments employing a transistor utilizing the body effect are disclosed.</p> |
