Sequential logic circuits implemented with inverter function logic

摘要

Sequential logic circuits are implemented with inverter function logic gates. In each circuit, level shifted transistor means are utilized in place of the standard reference transistors found in ECL gate circuits so that the complement of at least one of the input signals may be included in the logical operation performed by the sequential logic circuit. The complementary clock signal is thus not required as a separate input. Sequential logic functions thus implemented have fewer gates, less complex clock drivers, consume less power and have shorter propagation delay.