发明名称
摘要 In order to provide for substantially reduced costs in acceptance testing of aircraft computers, the acceptance test system described herein includes: a group of input circuits for receiving the computer output data signals; an input circuit adapted to receive signals from the aircraft computer representing the computer input data signals; and a transmitter for transmitting the computer input data to the computer. In this automatic acceptance test system, the computer under test generates both serial and parallel input data signals for itself which are then retransmitted to the computer under test by the automatic test system.
申请公布号 JPS6240739(B2) 申请公布日期 1987.08.29
申请号 JP19820159735 申请日期 1982.09.16
申请人 SANDOSUTORANDO DEETA KONTOROORU INC 发明人 JEIMUZU OBURAIEN
分类号 G06F11/22 主分类号 G06F11/22
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