| 摘要 |
A pulse frequency responsive switch includes a monoflop for receiving a pulse sequence. In response thereto, the monoflop generates a resulting square wave signal for application to an integration circuit and then a comparator. When the pulse rate of the pulse sequence exceeds the reciprocal of the relaxation time of the monoflop, the output therefrom assumes a steady D.C. voltage, which causes the comparator to generate an output signal for the pulse frequency responsive switch. This output signal is also used to lower the relaxation time of the monoflop, giving a hysteresis property to the pulse frequency responsive switch.
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