| 摘要 |
Disclosed is an improved bit selection circuit for a RAM, in particular one employing CTS (complementary transistor switch) cells. The bit select circuitry includes interconnected first and second level matrix decoders, each memory column has a pair of bit lines, each pair of bit lines has connected thereto a bit select circuit, each of the bit select circuits being connected to an output of the second level decoder, a bit up-level clamp circuit connected to each of the bit select circuits of each pair of bit lines, each of the bit select circuits including a first circuit for increasing the speed of selection of the selected pair of lines, the bit up-level clamp circuit cooperating with the bit select circuit of the selected pair of bit lines for positively limiting the upper potential level of the selected pair of bit lines, and each of the bit select circuits including a second circuit for increasing the speed of deselection of the selected pair of bit lines.
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