| 摘要 |
N stages of BCD adders receive as a first addend BCD encoded information representing a desired frequency. They receive as a second addend the outputs of N stages of four-bit registers. The summing outputs of the adders are input data for the registers. The data is clocked into the register by a stable frequency source. The outputs from a plurality of the most significant stages of the registers are used to address a ROM. Using the periodically changing BCD address, a sinusoidal function is retrieved in individual samples from the ROM. Digital data from the ROM is converted to analog. A low pass filter enhances the desired frequency and suitably attenuates higher frequencies. An equalizer compensates for power roll-off.
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