发明名称 Display deflection control loop
摘要 A system for synchronizing a succession of horizontal deflection coil currents of a CRT display with a succession of synchronization signals includes a variable delay which is strobed by a synchronization signal and triggers the generation of a deflection current after a specified delay. The delay is automatically controlled by a feedback loop in which the present delay is measured by a set-reset flip-flop, the flip-flop providing an output pulse having a duration equal to the delay. An integrator averages a train of output pulses from the flip-flop, and combines a reference signal with the average value to provide the control signal for the delay. The system operates with minimal bandwidth and with dynamics which are free of acquisition constraints so as to provide minimal sensitity to noise.
申请公布号 US4754330(A) 申请公布日期 1988.06.28
申请号 US19870077969 申请日期 1987.07.22
申请人 HAZELTINE CORPORATION 发明人 SPIETH, ROBERT H.
分类号 H04N5/12;(IPC1-7):H04N5/04 主分类号 H04N5/12
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