发明名称 SUCCESSIVE APPROXIMATION A-D CONVERTER
摘要 PURPOSE:To suppress an ideal quantization error within + or -LSB/2 without using a reference voltage of different polarity by providing a means forming a pseudo input, an output comparator, a correction memory, a successive comparison register and a means increasing the code of the successive comparator register by 1 so long as the content of the correction memory is 1. CONSTITUTION:A comparator CMP being a means forming a pseudo input quantity subtracting a value equivalent to LSB/2 from an input quantity to a DA converter compares the pseudo input quantity aud an output of the DA converter. Then the result is discriminated while codes of the DA converter are all 0. A value representing the absolute value of the input quantity larger by LSB/2 as 1 and smaller by it as 0 is stored in a correction memory. Only with the content of the correction memory set to 1, the digital code of the successive comparison register is incremented by 1. Thus, the ideal quantization error is kept within + or -LSB/2 without using a reference voltage of different polarity.
申请公布号 JPS63248221(A) 申请公布日期 1988.10.14
申请号 JP19870083364 申请日期 1987.04.03
申请人 NEC CORP 发明人 INUZUKA TERUO
分类号 H03M1/38 主分类号 H03M1/38
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