| 摘要 |
PURPOSE:To reduce an increase in the number of shift registers even when a clock cycle is shortened by providing a request shift register and a bank address shift register, and generating timing pulses with two signals transferred between those two shift registers. CONSTITUTION:This system is equipped with request shift registers SR0-SR6 which transfers a request signal to following registers in each clock cycle and bank address shift register SB0 and SB1 which transfer a bank address to following registers in each clock cycle of the minimum access interval between plural banks, and timing pulses are generated with the two signals transferred between those two kinds of shift registers. Consequently, the number of stages of shift registers is decreased, timing generation is performed optionally in every clock cycle, and even when the clock cycle is shortened, an increase in the number of shift registers is reduced.
|
