发明名称 DOUBLE CLOCK DEVICE WITH PHASE SYNCHRONIZATION
摘要 PURPOSE:To make accurately both frequency divider clocks generated by two circuit systems coincident with each other by giving a frequency divider clock generated by one circuit system to the 2nd phase comparison means of other circuit system and replacing the other circuit system into one circuit system. CONSTITUTION:A phase comparision frequency divider circuit 11 is arranged to an input side of a reference clock 10 constituting a double clock device with phase synchronization and a phase comparator frequency divider circuit 13 is arranged to the input side of the other clock 12. Moreover, switches 15, 16 are provided respectively between the circuits 11, 13 and the adder circuit 14 and a frequency variable circuit 17 is connected to the output side of the circuit 14. In constituting the circuit in this way, the frequency divider circuit 18 is provided to The output side of the circuit 17 and the circuits 11, 13 are connected to the output side. Thus, two switches are operated to activate the adder circuit thereby eliminating the phase difference of the frequency divider clock of the two circuit systems. That is, the one circuit system is made coincident with the other circuit system to make the phase difference of the frequency divider clock of both the systems zero.
申请公布号 JPS63288519(A) 申请公布日期 1988.11.25
申请号 JP19870122500 申请日期 1987.05.21
申请人 NEC CORP 发明人 MURATA HATSUO
分类号 H03L7/22 主分类号 H03L7/22
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