发明名称 TEST SYSTEM FOR THREE-PHASE CORRECTION CIRCUIT
摘要 PURPOSE:To facilitate the location at fault occurrence and to conduct test simply in the mounting state by setting a skew production state at a delay circuit forcibly so as to test a 3-phase correction circuit to be tested. CONSTITUTION:Since no skew is caused in applying write/read by the same head mechanism, the 2nd delay time (100% or over the write time interval, e.g., 150%) expecting the inversion of a binary data surely in a 3-phase generating circuit 7 is set to delay circuits (timers) 5, 6, a test data 50 is written on a magnetic stripe 30 and the written test data 50 is read. Thus, B and C phase data 52 retarded by 150% are generated and they are compared respectively with a 3-phase expected data 51 corresponding to the test data 50. When they are coincident, it is discriminated that the circuit is operated normal and in case of dissidence, abnormality display displaying the generated data is applied. Thus, the 3-phase correction circuit is tested in the mounting state.
申请公布号 JPS63311671(A) 申请公布日期 1988.12.20
申请号 JP19870148225 申请日期 1987.06.15
申请人 FUJITSU LTD 发明人 TSUBOI HIDEO
分类号 G11B20/18;G11B20/20 主分类号 G11B20/18
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