| 摘要 |
PURPOSE:To attain efficient debug and analysis even in a signal with many bit numbers by storing cyclicly sequentially a received serial data and a received frame synchronizing bit timing to a memory and reading the content of memory after the stop. CONSTITUTION:A write pulse of a memory 7 is generated by using a reception clock by a memory control circuit 8 and a received serial data and a received frame synchronizing bit are stored sequentially in the memory 7 for each reception clock and overwritten cyclicly in the memory 7 by the address till the memory control circuit detects the stop timing. Then the memory control circuit 8 brings a 2-way driver 9 into the output enable state by the memory control circuit 8 and the content of the next address to the address written finally is read in the memory 7. Thus, the received serial data and the frame synchronizing bit timing stored in the memory 7 are all readable and the analysis by 64k bits is facilitated back from the stopped reception serial data depending on the stop condition.
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