TMS/TDI and SIPO controller circuitry with tap and trace interfaces

摘要

An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

主权项

1. An integrated circuit, comprising:
(a) test access port circuitry having a TDI input lead, a TMS input lead, a TCK input lead, a TDO output lead, a trace data output, a trace data input, and a trace control output; (b) trace domain circuitry having trace control inputs, a trace clock input, and a trace data output; and (c) controller circuitry having a TMS/TDI input lead, a clock input lead, and a TDO input lead, the controller circuitry being connected to:
i. the test access port circuitry by a TDI output lead coupled to the TDI input lead, a TMS output lead coupled to the TMS input lead, a TCK output lead coupled to the TCK input lead, and a TDO input lead coupled to the TDO output lead of the test access port circuitry; andii. the trace domain circuitry by trace control outputs coupled to the trace control inputs, a trace clock output coupled to the trace clock input, and a trace data input coupled to the trace data output; and (d) the controller circuitry including:
(i) serial input parallel output circuitry having a serial input connected to the TMS/TDI input lead, a clock input connected with the clock input lead, a TDI output, and a TMS output;(ii) a TDI update register having an input connected to the TDI output of the serial input parallel output circuitry and an output connected to the TDI output lead; and(iii) a TMS update register having an input connected to the TMS output of the serial input parallel output circuitry and an output connected to the TMS output lead.