Integrated circuit with distributed clock tampering detectors

摘要

A circuit configuration for secure application includes several internal frequency detectors arranged in digital units at critical points of an integrated circuit. The clock detectors are concealed in the digital part of the integrated circuit each as a standard cell (flip-flop unit) in order to prevent any external manipulation and in order to hide its function. The clock detectors are preferably disposed in a clock tree topology, which can be at several levels for distributing the clock signal through the different digital unit tree at critical points. Alarms are generated via a clock detector network if at any level an external clock attack has been monitored.

主权项

1. A circuit configuration for detecting external manipulation of a clock in an integrated circuit comprising digital units and at least one clock detector monitoring frequency and duty cycle parameters of a clock signal, where in case of a deviation of either frequency or of a duty cycle parameter an alarm signal is generated at an output of said at least one clock detector, said configuration comprising:
an arrangement of a plurality of clock detectors at critical points of the integrated circuit, said critical points being integrated in at least one portion of a digital unit of a digital block, which is clocked by a clock signal from an analog block, wherein the plurality of clock detectors are concealed in a digital block as standard cells, which each comprise a set of transistors interconnected together to implement a Boolean or a storage logic function in said integrated circuit.