发明名称 Coder/decoder for time compressed integration system
摘要 A coder/decoder for a time compressed integration system includes a coder for performing time compressed ingtegration of compressed wide- and narrow-width chrominance signals and a luminance signal having passed through a first phase compensation delay circuit and outputting a time compressed integration (TCI) signal, and a decoder for decoding the luminance signal and the chrominance signals from the TCI signal. The coder and the decoder are substantially arranged on a single LSI chip. The coder/decoder includes a first and a second memory section. In a coder mode, the first memory section serves as the first phase compensation delay circuit and part of the second memory section serves as the tapped delay devices in the vertical filters. In a decoder mode, the first memory section and one part of the second memory section serve as a second phase compensation delay circuit, and the other part of the second memory section serves as a tapped delay device in an interpolation filter.
申请公布号 US4858004(A) 申请公布日期 1989.08.15
申请号 US19880146188 申请日期 1988.01.20
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 KITAGAKI, KAZUKUNI;OHTO, TAKESHI
分类号 H04N11/04;H04N11/08;H04N11/10;H04N11/24 主分类号 H04N11/04
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