| 摘要 |
<p>A high speed processor (12) is disclosed for use in conjunction with a main processor (10) of a computer system. In the computer system, one program is being executed. The high speed processor executes certain selected instructions of the one program which are designated more frequently executed than the remaining instructions of the one program. The main processor executes the remaining instructions of the one program when the high speed processor is not executing the selected instructions. In addition, the high speed processor executes the selected instructions more rapidly than would be the case if the main processor were to execute the selected instructions. The high speed processor executes the selected instructions more rapidly due to the fact that it operates in an <<overlap execution mode>>. In this overlap mode, the high speed processor is preparing the next instruction for execution simultaneously with the execution of the current instruction. However, an address compare circuit (12c4) disposed within the high speed processor ensures that the execution of the current instruction is completed prior to the commencement of the execution of the next instruction. In addition, a special retry buffer (12c5) is provided in the event the execution of the instruction should be repeated. As a result of the utilization of the high speed processor in conjunction with the main processor for the execution of the instructions of one program, the instruction processing time is decreased by a factor of approximately forty (40) percent. Therefore, the performance of the computer system has been optimized.</p> |
