| 摘要 |
FIELD: computer engineering.SUBSTANCE: memory controller for controlling access to a memory device of the type having a non-uniform access timing characteristic has an interface for receiving transactions issued from at least one transaction source; a buffer used to temporarily store as pending transactions those transactions that have not yet been issued to the memory device, wherein the buffer maintains a plurality of ordered lists for the stored pending transactions, including at least one priority based list, and at least one access timing list, wherein each priority based ordered list has a number of entries, each entry is associated with one of the pending transactions and ordered within its priority based ordered list based on the priority indication of the associated pending transaction; arbitration circuitry that performs an arbitration operation during which the plurality of ordered lists are referenced so as to select from the pending transactions a winning transaction to be issued to the memory device.EFFECT: to achieve a balance between reordering of transactions to improve memory access times.28 cl, 21 dwg |
