| 摘要 |
The arrangement incorporates multiple levels of patterned conductors. Upper and lower patterned conductors are situated on an insulation- coated, monocrystalline silicon substrate. Upper and lower, higher resistivity, polycrystalline silicon layers, in turn, are situated on the first level upper and lower patterned conductors, respectively. Second level upper and lower patterned conductors are situated over the upper and lower polycrystalline silicon layers. Further levels of patterned conductors in the circuit board may be provided by iteratively forming on the board polycrystalline silicon layers and patterned conductors. Conducting feedthroughs in the circuit board provide electrical communication between various patterned conductors. |
