Synchroniser flip-flop

摘要

A synchronizer flip-flop is provided, which is able to better respond to input values that are not provided for the necessary setup or hold times. The flip-flop includes a latch that includes inverter circuitry for producing a first signal and a signal in dependence on a value of an input signal at a node. A clocked inverter includes a first switch that is connected between a first reference voltage supply and an intermediate node and a second switch, which is connected between the intermediate node and a second reference voltage supply. The first switch is controlled by the first signal and the second switch is controlled by the second signal to produce an output signal at the intermediate node.

主权项

1. A synchroniser flip-flop comprising:
a latch comprising:
inverter circuitry to produce a first signal and a second signal in dependence on a value of an input signal at a node; anda clocked inverter comprising:
a first switch connected between a first reference voltage supply and an intermediate node; anda second switch connected between the intermediate node and a second reference voltage supply, wherein the first switch is controlled by the first signal and the second switch is controlled by the second signal to produce an output signal at the intermediate node; and a further latch connected in series with the latch, the further latch comprising:
further inverter circuitry to produce a further first signal and a further second signal in dependence on a value of a further input signal at a further node; anda further clocked inverter comprising:
a further first switch connected between the first reference voltage supply and a further intermediate node; anda further second switch connected between the further intermediate node and the second reference voltage supply, wherein the further first switch is controlled by the further first signal and the further second switch is controlled by the further second signal to produce a further output signal at the further intermediate node, and wherein the further input signal at the further node is dependent on the further output signal at the further intermediate node.