VERTICAL ADRESS GENERATING CIRCUIT FOR PIP TELEVISION

摘要

The circuit displayes subpicture not decreasing vertical resolution using tri-frequency divider, 8-bit counter, control logic and an even/odd detection circuit. A tri-frequency divider condences vertical width of subpicture and the output of the tri-frequency divider is input to a clock terminal of a counter through logic gate according to even and odd field. Even and odd field is discriminated by a D flip-flop and are utilized as gating and loading signal of the tri-frequency and the counter.