Signal processor with independently arithmetic and logic unit and multiplier accumulator unit simultaneously operable.

摘要

The architecture of the signal processor operates the ALU (10) and MACU (11) through a register file (9) that serves as a general buffer pool for operands. All operand transfers take place between data memory through this register file (9) and ALU (10) and MACU (11) have equal access to all data in the file (9). Further the file (9) is the buffer for previous ALU results. In this manner, the bandwidths of all the individual units, data buses (19, 20), ALU (10) and MACU (11) can be fully utilized without conflicts. In general, the proposed configuration relies on the redundance or latency in many signal processing computations where data and results are used and reused in the overall computation and must remain in holding registers. The register file gives this capability providing these operands for use independently by both the ALU (10) and MACU (11). Without a common register file, operands would have to be reloaded as the computation continues. These redundant loads reduce the throughput for the computation.