ENHANCED LOCKED BUS CYCLE CONTROL IN A CACHE MEMORY COMPUTER SYSTEM

摘要

ENHANCED LOCKED BUS CYCLE CONTROL IN A CACHE MEMORY COMPUTER SYSTEM An enhanced processor lock cycle management system for computer systems including a processor 10 and a cache memory controller 12 which accommodates existing methodologies and provides an enhanced mode wherein processor lock cycles are not passed to the controller 12 but control of the system bus 14 by controller 12 is maintained by inhibiting hold requests to the controller 12 by other system elements.