| 摘要 |
An analog/digital converter configuration includes sigma-delta modulators being triggered by an analog input signal and emitting digital output signals at a predetermined sampling rate. The sigma-delta modulators have input circuits with amplification factors. Amplifiers are each connected upstream of a respective one of the sigma-delta modulators. First sampling rate reducers are each connected downstream of a respective one of the sigma-delta modulators. Damping elements are each connected downstream of a respective one of the first sampling rate reducers. Each of the damping elements have a damping factor equal to the inverse of the amplification factor occurring in the input circuit of a corresponding one of the sigma-delta modulators. A priority logic is connected downstream of the damping elements. A second sampling rate reducer is connected downstream of the priority logic. An output is connected downstream of the second sampling rate reducer. The priority logic switches a signal from the first sampling rate reducers to the output after evaluation of signals from the first sampling rate reducers.
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