High-speed convolutional decoder

摘要

A convolutional decoder for decoding a received message of digital data convolutionally encoded at a constraint length of K, comprises branch metric calculating circuitry for receiving the data and providing output signals indicative of the branch metrics therefor, a plurality of 2K-1 circuits for receiving the output signals and computing state metrics, the circuits being interconnected to form a trellis and generating decision bits and a plurality of 2K-1 memory circuits, the memory circuits being interconnected also to form a trellis and responsive to the decision bits to output a decoded digit of the received message data.