| 摘要 |
The vertical run length smoothing alogrithm is realized using a hardware so that processing time is minimized. The system includes an address generator (100) for generating a first address of run length, a data generator (200) for comparing contents in the address to limit value so that pixel counting is continued or a black pixel is replaced by a white pixel, a data comparing unit (300) for comparing counted number of pixel to set the system read mode or write mode, and an address detector (400) for detecting an address from which a first "1" is started.
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