| 摘要 |
To be able to load an ATM switching network as efficiently as possible, the successive cells of one and the same connection are routed to the output by as many different paths as possible; however, mutual overtaking of successive cells must be avoided or corrected. Each cell is held at the output until it is certain that no older cell can be buffered in the switching network. Before the cell is passed on, a check is made to determine whether the cells received from the switching network later include an older cell which must be passed on before that cell. At the input end, consecutive numbers ("Sequence Numbers") are allocated to the cells. A buffer (1) at the output end is operated, at least in part (1 . . . d), in the manner of a shift register, thereby introducing a predetermined delay. Prior to the output of a cell, at least the shift-register-like portion of the buffer is examined as to whether a cell written in later is to be put out earlier: if so, the two cells are interchanged.
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