| 摘要 |
<p>A digital testing system for testing very high frequency phase-locked loop. The loop (2) is configured in a selected mode by way of an interface, a digital input pattern is applied to an input terminal, signal information internal to the phase-locked loop is accessed through the interface and the information is extracted and interpreted with a digital tester. Various dynamic characteristics such as clock jitter, acquisition time, step response, window truncation and static alignment error may be tested. <IMAGE></p> |
