Multi-CPU programmable controller.

摘要

A multi-CPU programmable controller operates to access one of a plurality of I/O interface units through a common I/O bus for controlling one of a plurality of equipments connected to the I/O units. The system comprises a pair of controller units with individual CPUs which operate in accordance with specific programs independently from each other such that each controller unit generates an access signal to access one of the I/O units for controlling the associated equipment within one bus cycle. The controller units, I/O bus and I/O units are mounted on a single base board. The board includes a bus arbitrator having a sampling clock and supervising access signals from the two controller units to determine based upon a timing of the sampling clock which of the controller units is first to generate the access signal when the access signals are received within the one bus cycle from the two controller units, thereby giving priority to one of the two controller units over the other. The bus arbitrator allows to the one prior controller unit to use the I/O bus and access the corresponding I/O unit while stalling the other controller unit so long as the latter generates the access signal within the bus cycle during which the prior controller units accesses the corresponding I/O unit, and allows the other controller unit to use the I/O bus and access the corresponding I/O units upon completion of the access from the prior controller unit. <IMAGE>