| 摘要 |
<p>PURPOSE:To shorten the processing time for abnormality detection of a memory device. CONSTITUTION:When detecting the abnormality of a memory part 3, a memory control part 1 outputs an address signal 101 and an abnormality detection signal 102 to an address control part 2. When the abnormality detection signal 102 is inputted from the memory control part 1, the address control part 2 validates all of memory blocks 3-1 to 3-3 and outputs a lower address signal 120 to memory blocks 3-1 to 3-3 in common. Data is simultaneously read from or written in memory blocks 3-1 to 3-3 by the lower address signal 120 from the address control part 2. An exclusive OR circuit 4 operates exclusive OR among data signals 131 to 133 read out from memory blocks 3-1 to 3-3 and reports the operation result to the memory control part 1 by an operation result signal 141.</p> |
