发明名称 |
Contact alignment for read only memory devices. |
摘要 |
<p>A layout and fabrication technique for EPROMs and similar devices includes a preferred technique for partially self-aligning bit line contacts. In addition, a self-aligned, buried Vss line is provided which is in contact with the substrate for its entire length. This provides a highly conductive Vss line, allowing the size of such line to be diminished. The use of a buried Vss contact line and a partially self-aligned bit line contact contributes to a device layout having minimum cell sizes for a given feature size. <IMAGE></p> |
申请公布号 |
EP0528690(A1) |
申请公布日期 |
1993.02.24 |
申请号 |
EP19920307596 |
申请日期 |
1992.08.20 |
申请人 |
SGS-THOMSON MICROELECTRONICS, INC. |
发明人 |
BRYANT, FRANK RANDOLPH;CHAN, TSIU CHIU |
分类号 |
G11C17/00;H01L21/768;H01L21/8247;H01L27/115;H01L29/788;H01L29/792 |
主分类号 |
G11C17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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