| 摘要 |
PURPOSE:To detect break of a common clock signal on a system bus to prevent the occurrence of system down by providing a common clock signal break detecting circuit in electronic circuit parts connected to the system bus. CONSTITUTION:A common clock signal C1 on a system bus 3 is inputted to a system bus interface 12, a common clock signal break detecting circuit 16, and a clock signal disaccord detecting circuit 17, and a local clock signal C2 from a clock signal generating circuit 15 is inputted to the circuit 17. A clock break detection signal S1 from the circuit 16, a disaccord detection signal S2 from the circuit 17, and the clock signal C2 from the circuit 15 are inputted to a clock transmission control circuit 18, and the output from this circuit 18 is connected to the common clock signal C1 on the bus 3 by wired OR. Thus, only one common clock signal is allowed to always exist on the system bus without using a private common clock signal supply circuit like a bus management circuit to improve the reliability of the circuit. |
