发明名称
摘要 <p>PURPOSE:To constitute the titled system so that plural virtual computers can execute processing with each individual time, by holding a difference between a set time and a real time, in a prescribed register, and correcting a value of a real clock by a value of this register. CONSTITUTION:When an SCK instruction is issued in the course of execution of a virtual computer, a difference which has subtracted a tie value of that time which is held by a clock 5, from a time set value designated by an instruction which is sent out to a signal line 32 is calculated by a subtracting circuit 21, and set to a corrected value register 20. Thereafter, when an STCK instruction is executed, a value of the correction register 20 is added by an adding circuit 23 to a time value of the clock 5 which is outputted to a signal line 10, and its sum is stored as the present time value in a main storage area designated by the instruction. Accordingly, the value of the corrected value register 20 is saved at every virtual computer, and when the control is delivered to the virtual computer, the saved value is loaded to the corrected value register 20, by which each virtual computer can have each individual time.</p>
申请公布号 JPH0520774(B2) 申请公布日期 1993.03.22
申请号 JP19850248271 申请日期 1985.11.06
申请人 FUJITSU LTD 发明人 KANEDA SABURO;MURAKAMI KAZUAKI
分类号 G06F9/46;G06F1/04;G06F1/14 主分类号 G06F9/46
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