High-precision D=A converter with decoder - adds weighted contributions from sample=and=hold circuits associated with data bits read from buffer memory

摘要

A number of sample-and-hold circuits (SH0-SH4) is loaded (SL0-SL4) with signal values of min. tolerance to generate precise currents or voltages corresp. to different bits of the binary word (A0-A4) input to a decoder and buffer store (ZwS). The outputs (B0-B4) operate respective switches (S0-S4) which connect the contents of the sample-and-hold circuits (SH0-SH4) to decoupling amplifiers (V0-V4) driving a summation circuit (sigma). A least-significant-bit current (10) is added (sigma L) to the sum. USE/ADVANTAGE - In e.g. digital audio signal processing, higher overall precision is achieved economically without need to allow for loss in digitisation dynamics.