| 摘要 |
<p>An embodiment of the present invention is a 1,024 by 1,024 DRAM (77) integrated with a 1,024 by one SRAM (61). The SRAM (61) contents can be directly addressed by external memory accesses and will services data transfers much faster than the DRAM (77) could. The SRAM carries 64 lines of 16-bits (63) of DRAM data. When an external write or read addresses a line of DRAM (77) not in the SRAM (61), the SRAM (61) flushes a line to update a previously cached line of DRAM (77), and then downloads a line of DRAM that contains a currently requested data bit. <IMAGE></p> |
