| 摘要 |
<p>A digital adder module (M1) has a carry-in terminal (12), N pairs of data terminals (10 and 11), N sum terminals (S1-S4), and a carry-out terminal (16). A high-speed low-capacitance carry bypass signal path couples the carry-in terminal to the carry-out terminal. In one preferred embodiment, the capacitance of the bypass path is due solely to one transistor channel (T11) plus one transistor drain (T10) plus one internal logic gate (I1) plus interconnections between them.</p> |
