| 摘要 |
The method and apparatus can be used in the design of integrated circuits for associative memories. This method and apparatus ease the design process and increase the speed of associative data processing. The method involves transferring the contents of the associative memory correspondence register where associative operations are performed to the remainder of the associative memory (which is involved in the expansion of the associative word) within one or more clock cycles via one or more buses. The apparatus includes a transfer control unit (1), a first group of input/output control buses for associative memory (2); this group is connected to counter (3) via a second group of input/output buses. The first group of outputs is interfaced to the data multiplexer (4), while the second group of outputs is interfaced to data buffer (5), and the third group of outputs is interfaced to correspondence register (6). The output group from counter (3) is interfaced to data multiplexer (4), which is in turn interfaced (through the first group of counter input/output buses) to data buffer (5), the second group of counter input/output buses is interfaced to data multiplexer (4); the first group of input/output buses from the data multiplexer is interfaced to data buffer (5), the second group of input/output buses is interfaced to input/output register unit (7), and the rest of the input/output bus groups are interfaced to correspondence register (6). The second input/output bus group to data buffer (5) is data bus (8) for the associative memory.<IMAGE>
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