| 摘要 |
PURPOSE: To enable contacts commonly used by a large number of cells and to minimize a size of a chip by forming in a method, which has an advantage of source side infusion and can be used in an ideal ground embedded type bit- line array layout. CONSTITUTION: A floating gate 14, made of polycrystalline silicon is formed on a tunnel oxide film 12 which is formed between separating regions of a field oxide film on a substrate and a layer with an oxide film, a nitride film and an oxide film (ONO), is formed thereon. An oxide film 18 is provided on a sidewall of the floating gate 14 and a gate oxide film 16 is formed adjacent on the substrate. After that an N<+> -drain inclined junction is formed at the drain side on the substrate, and a spacer 20 made of polycrystalline silicon which is relatively junctioned in an X-direction at the periphery of the floating gate 14 by grouping a source 22 and a drain 24 of each cell. After that, a control gate 28 is formed on the floating gate 14 and the spacer 20 by separating with the ONO and an oxide film 26. |
