IMPROVED VGA CONTROLLER HAVING FRAME BUFFER MEMORY ARBITRATION AND METHOD THEREFOR

摘要

An improved VGA Controller (10) with Arbitration Logic (24) and method therefor is provided to enhance system performance by efficiently using the minimum amount of bus bandwidth required. This Controller (10) includes a bus (18) to the Frame Buffer (14) that either the system CPU (12) or the Display Controller (16) may access and control. The Display Controller (16) includes a Display FIFO (28) which stores display data from the Frame Buffer (14) for the Display Controller (16) to use. This Display FIFO (28) coupled with the Arbitration Logic (24) makes it possible for the Display Controller (16) to continue to output display data even when the system CPU (12) is accessing the display data in the Frame Buffer (14). The Arbitration Logic (24) attempts to keep the Display FIFO (28) as full as possible such that a bus request by the system CPU (12) can be immediately granted when received.