发明名称 |
COMMUNICATION BUS FOR D-CHANNEL INFORMATION OPERATION |
摘要 |
This system provides an interprocessor communication bus to perform a multi-bus structure and a function of bus control section. In a subscriber mode of ISDN being comprised one master node and multi-slave nodes, and in interprocessor communication means sending signal and data clock for information transmission, the bus includes a clock loop line (a) which provides the control clock to the slave nodes, the 1st data loop line (b) which provides data from the master node to the slave nodes, and the 2nd data loop line (c) which provides data from the slave nodes to the master node.
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申请公布号 |
KR940000179(B1) |
申请公布日期 |
1994.01.08 |
申请号 |
KR19900016051 |
申请日期 |
1990.10.10 |
申请人 |
KOREA ELECTRONICS & TELECOMMUNICATIONS RESEARCH INSTITUTE;KOREA TELECOMMUNICATIONS CORP. |
发明人 |
SO, CHANG - JIN;KIM, MYONG - SOK;LEE, SUNG - HUI;SON, DONG - CHOL;JONG, HUI - CHANG |
分类号 |
H04L12/12;(IPC1-7):H04L12/12 |
主分类号 |
H04L12/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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