发明名称 |
Cache memory and bus width control circuit for selectively coupling peripheral devices |
摘要 |
A bus width control circuit being arranged between a first bus and a second bus both of n-bits width, and comprising a buffer group being connected to the first bus and which split data of n-bits into partial data of m-bits and buffer them, a selector which connects each buffer to the second bus in parallel in the case where the effective data bus width of the second bus is n bits and which connects each buffer to a predetermined m bits of the second bus in the case where the effective data bus width of the second bus is m bits, and a control circuits thereof, and a control circuit which locates intact the n-bits data of the first bus in the second bus or by splitting it into partial data of m-bits in a predetermined portion of n-bits data and outputs them sequentially to the second bus, or which splits the n-bits data of the second bus into partial data of m-bits and buffers them in each buffer and then simultaneously outputs them to the first bus, or which sequentially buffers data whose m bits alone of the second bus is effective into each buffer and then simultaneously outputs them to the first bus.
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申请公布号 |
US5280598(A) |
申请公布日期 |
1994.01.18 |
申请号 |
US19910717779 |
申请日期 |
1991.06.17 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
OSAKI, AKITOSHI;NISHIDA, KOICHI |
分类号 |
G06F12/08;G06F13/36;G06F13/40;(IPC1-7):G06F12/08;G06F12/04 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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