Data transmission apparatus and method for transmitting data in delay-insensitive data transmission method supporting handshake protocol

摘要

Provided are a data transmission apparatus and method for transmitting data in a Delay-Insensitive (DI) data transmission method supporting a handshake protocol. The data transmission apparatus includes a sender which outputs a binary-valued logic signal based on binary-valued logic, and an encoder which encodes the binary-valued logic signal input through input wires into a multi-valued logic signal based on multi-valued logic and transmits the encoded multi-valued logic signal to a decoder through output wires. Here, the encoder includes a mapping table which stores input variables including the number of input wires and the number of output wires smaller than the number of input wires and the multi-valued logic signal corresponding to the input variables, and encodes the binary-valued logic signal into the multi-valued logic signal with reference to the mapping table.

主权项

1. A data transmission apparatus for transmitting data in a Delay-Insensitive (DI) data transmission method supporting a handshake protocol, the data transmission apparatus comprising:
a sender configured to output a binary-valued logic signal based on binary-valued logic; and an encoder configured to encode the binary-valued logic signal input through input wires into a multi-valued logic signal based on multi-valued logic, and transmit the encoded multi-valued logic signal to a decoder through output wires, wherein the encoder includes a mapping table storing input variables including a number of input wires and a number of output wires smaller than the number of input wires and the multi-valued logic signal corresponding to the input variables, and encodes the binary-valued logic signal into the multi-valued logic signal with reference to the mapping table, and wherein the encoder extracts a logic combination of the binary-valued logic signal expressed according to the number of input wires and the multi-valued logic signal mapped to the number of output wires with reference to the mapping table, and encodes the binary-valued logic signal into the extracted multi-valued logic signal.