Sensing and responding to invalid states in logic circuitry

摘要

In order to prevent a logic circuit including a multi-stage temporary storage array having both valid and invalid state combinations from locking up in an inadvertently entered invalid state and from alternating between invalid state combinations, support logic circuitry is employed which is configured to force the array back to a valid state combination. The forcing operation may be alternatively undertaken immediately or in synchronism with the next succeeding clock pulse following entry into the invalid state combination. A specific valid state combination to be entered following entry into a specific invalid state may be predetermined.